EZ80F91MCU Datasheet, PDF (111/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
92
System Clock
ADDR[23:0]
S0
S1
S2
S3
S4
S5
S6
S7
DATA[7:0]
CSx
AS
DS
R/W
DTACK
MREQ
or IORQ
Figure 18. Motorola Bus Mode Write Timing Example
Switching Between Bus Modes
When switching bus modes between Intel™ to Motorola, Motorola to Intel™, eZ80
to Motorola, or eZ80 to Intel™, there is one extra SCLK cycle added to the bus
access. An extra clock cycle is not required for repeated access in any of the bus
modes (for example Intel™ to Intel™). An extra clock cycle is not required for
Intel™ (or Motorola) to eZ80 bus mode (under normal operation). The extra clock
cycle is not shown in the timing examples. Due to the asynchronous nature of
these bus protocols, the extra delay does not impact peripheral communication.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States