EZ80F91MCU Datasheet, PDF (102/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
83
Table 20. Intel Bus Mode Read States—Separate Address and Data Buses (Continued)
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven
Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait
states (T_WAIT) are asserted until the READY pin is driven High.
The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel bus mode cycle.
During Write operations with separate address and data buses, the Intel bus
mode employs 4 states—T1, T2, T3, and T4—as described in Table 21.
Table 21. Intel Bus Mode Write States—Separate Address and Data Buses
STATE T1
STATE T2
STATE T3
STATE T4
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted, and the data is driven onto the data bus. The
CPU drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU
drives ALE Low to facilitate the latching of the address.
During State T2, the CPU asserts the WR signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven
Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait
states (T_WAIT) are asserted until the READY pin is driven High.
The CPU deasserts the WR signal at the beginning of State T4. The CPU holds the data
and address buses through the end of T4. The bus cycle is completed at the end of T4.
Intel™ bus mode timing is illustrated for a Read operation in Figure 12 and for a
Write operation in Figure 13. If the READY signal (external WAIT pin) is driven
Low prior to the beginning of State T3, additional wait states (T_WAIT) are asserted
until the READY signal is driven High. The Intel bus mode states can be config-
ured for 2 to 15 CPU system clock cycles. In the figures, each Intel™ bus mode
state is 2 CPU system clock cycles in duration. Figures 12 and 13 also illustrate
the assertion of one wait state (T_WAIT) by the selected peripheral.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States