EZ80F91MCU Datasheet, PDF (375/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
356
Wait State Timing for Write Operations
Figure 69 illustrates the extension of the memory access signals using a single
WAIT state for a Write operation. This wait state is generated by setting CS_WAIT
to 001 in the Chip Select Control Register.
T_CLK
PHI
T_WAIT
ADDR[23:0]
DATA[7:0]
(output)
CSx
MREQ
WR
Figure 69. Wait State Timing for Write Operations
PS019209-0504
PRELIMINARY
Electrical Characteristics