EZ80F91MCU Datasheet, PDF (162/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
143
Table 58. Timer Data Register—High Byte
(TMR0_DR_H = 0064h, TMR1_DR_H = 0069h, TMR2_DR_H = 0073h,
TMR3_DR_H = 0078h)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
Value Description
[7:0]
TMR_DR_H
00h–FFh These bits represent the High byte of the 2-byte timer data
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 15
(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit
timer data value.
Timer Reload Register—Low Byte
The Timer x Reload Register—Low Byte, detailed in Table 59, stores the least-sig-
nificant byte (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the
timer reload value is reloaded into the timer upon end-of-count. When the reload
bit (TMRx_CTL[RLD]) is set to 1 forcing the reload function, the timer reload value
is written to the timer on the next rising edge of the clock.
This register shares its address with the corresponding timer data register.
Table 59. Timer Reload Register—Low Byte
(TMR0_RR_L = 0063h, TMR1_RR_L = 0068h, TMR2_RR_L = 0072h,
TMR3_RR_L = 0077h)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
TMR_RR_L
Value Description
00h–FFh These bits represent the Low byte of the 2-byte timer
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of
the 16-bit timer reload value.
PS019209-0504
PRELIMINARY
Programmable Reload Timers