EZ80F91MCU Datasheet, PDF (155/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
136
Table 53. GPIO Mode Selection When Using Timer Pins (Continued)
Port
B
GPIO Port GPIO Port
Bits
Mode
PB0
7
PB1
7
PB4
7
PB5
7
Timer Function
PWM_CTL1
MPWM_EN = 0
PWM_CTL1
MPWM_EN = 1
IC0/EC0
IC1
IC2
IC3
Timer Registers
The CPU monitors and controls the timer using seven 8-bit registers. These regis-
ters are the control register, the interrupt identification register, the interrupt
enable register and the reload register pair (High and Low byte). There are also a
pair of data registers used to read the current timer count value.
The variable x can be 0, 1, 2, or 3 to represent each of the 4 available timers.
Basic Timer Register Set
Each timer requires a different set of registers for configuration and control. How-
ever, all timers contain the following seven registers, each of which is necessary
for basic operation:
• Timer Control Register (TMRx_CTL)
• Interrupt Identification Register (TMRx_IIR)
• Interrupt Enable Register (TMRx_IER)
• Timer Data Registers (TMRx_DR_H and TMRx_DR_L)
• Timer Reload Registers (TMRx_RR_H and TMRx_RR_L)
The Timer Data Register is Read Only, while the Timer Reload Register is Write
Only. The address space for these two registers is shared.
Register Set for Capture in Timer 1
In addition to the basic register set, Timer 1 uses the following five registers for its
INPUT CAPTURE mode:
• Capture Control Register (TMR1_CAP_CTL)
• Capture Value Registers (TMR1_CAP_B_H, TMR1_CAP_B_L,
TMR1_CAP_A_H, TMR1_CAP_A_L)
PS019209-0504
PRELIMINARY
Programmable Reload Timers