EZ80F91MCU Datasheet, PDF (56/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
37
Table 3. Register Map (Continued)
Address
(hex) Mnemonic
Name
Reset
CPU Page
(hex) Access #
Ethernet Media Access Controller, continued
0034 EMAC_HTBL_1
EMAC Hash Table—Byte 1
00
R/W 264
0035 EMAC_HTBL_2
EMAC Hash Table—Byte 2
00
R/W 264
0036 EMAC_HTBL_3
EMAC Hash Table—Byte 3
00
R/W 264
0037 EMAC_HTBL_4
EMAC Hash Table—Byte 4
00
R/W 264
0038 EMAC_HTBL_5
EMAC Hash Table—Byte 5
00
R/W 264
0039 EMAC_HTBL_6
EMAC Hash Table—Byte 6
00
R/W 264
003A EMAC_HTBL_7
EMAC Hash Table—Byte 7
00
R/W 264
003B EMAC_MIIMGT
EMAC MII Management Register
00
R/W 265
003C EMAC_CTLD_L
EMAC PHY Configuration Data—Low
00
Byte
R/W 266
003D EMAC_CTLD_H
003E
003F
EMAC_RGAD
EMAC_FIAD
EMAC PHY Configuration Data—High 00
Byte
EMAC PHY Register Address Register 00
EMAC PHY Unit Select Address
00
Register
R/W 267
R/W 267
R/W 268
0040 EMAC_PTMR
EMAC Transmit Polling Timer Register 00
R/W 268
0041 EMAC_RST
EMAC Reset Control Register
00
R/W 269
0042 EMAC_TLBP_L
EMAC Transmit Lower Boundary
Pointer—Low Byte
00
R/W 270
0043
0044
0045
0046
EMAC_TLBP_H
EMAC_BP_L
EMAC_BP_H
EMAC_BP_U
EMAC Transmit Lower Boundary
00
Pointer—High Byte
EMAC Boundary Pointer—Low Byte
00
EMAC Boundary Pointer—High Byte
C0
EMAC Boundary Pointer—Upper Byte FF
R/W 270
R/W 271
R/W 271
R/W 272
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
out reset, the Watch-Dog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read Only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a
an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.
5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
PS019209-0504
PRELIMINARY
Register Map