EZ80F91MCU Datasheet, PDF (113/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
94
Chip Select x Upper Bound Register
For Memory Chip Selects, the Chip Select x Upper Bound registers, detailed in
Table 27, defines the upper bound of the address range for which the correspond-
ing Chip Select (if enabled) can be active. For I/O Chip Selects, this register pro-
duces no effect. The reset state for the Chip Select 0 Upper Bound register is FFh,
while the reset state for the other Chip Select upper bound registers is 00h.
Table 27. Chip Select x Upper Bound Register
(CS0_UBR = 00A9h, CS1_UBR = 00ACh, CS2_UBR = 00AFh, CS3_UBR = 00B2h)
Bit
7
6
5
4
3
2
1
0
CS0_UBR Reset
1
1
1
1
1
1
1
1
CS1_UBR Reset
0
0
0
0
0
0
0
0
CS2_UBR Reset
0
0
0
0
0
0
0
0
CS3_UBR Reset
0
0
0
0
0
0
0
0
CPU Access
R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSX_UBR
Value Description
00h–
FFh
For Memory Chip Selects (CSX_IO = 0)
This byte specifies the upper bound of the Chip Select
address range. The upper byte of the address bus,
ADDR[23:16], is compared to the values contained in these
registers for determining whether a Chip Select signal should
be generated.
For I/O Chip Selects (CSx_IO = 1)
No effect.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States