EZ80F91MCU Datasheet, PDF (300/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
281
EMAC Receive Write Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC
Receive Write Pointer Register are always zero.
Table 177. EMAC Receive Write Pointer Register—High Byte
(EMAC_RWP_H = 0052h)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
[7:0]
EMAC_RWP_H
Value
00h–
1Fh
Description
These bits represent the High byte of the 2-byte EMAC
RxDMA Receive Write Pointer value, {EMAC_RWP_H,
EMAC_RWP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit
0 is bit 8 of the 16-bit value.
EMAC Transmit Read Pointer Register—Low Byte
The Low byte of the Transmit Read Pointer register reports the current TxDMA
Transmit Read pointer.This pointer is initialized to EmacTLBP whenever
Emac_RST bits SRST or HRRTN are set. Because the size of the packet is lim-
ited to a minimum of 32 bytes, the last five bits are always zero. See Table 178.
Table 178. EMAC Transmit Read Pointer Register—Low Byte
(EMAC_TRP_L = 0053h)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
Value
[7:0]
00h–
EMAC_TRP_L E0h
Description
These bits represent the Low byte of the 2-byte EMAC
TxDMA Transmit Read Pointer value, {EMAC_TRP_H,
EMAC_TRP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit 0
(lsb) of the 16-bit value.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller