EZ80F91MCU Datasheet, PDF (210/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
191
UART Registers
After a system reset, all UART registers are set to their default values. Any Writes
to unused registers or register bits are ignored and reads return a value of 0. For
compatibility with future revisions, unused bits within a register should always be
written with a value of 0. Read/Write attributes, reset conditions, and bit descrip-
tions of all of the UART registers are provided in this section.
UART Transmit Holding Register
If less than eight bits are programmed for transmission, the lower bits of the byte
written to this register are selected for transmission. The Transmit FIFO is
mapped at this address. The user can write up to 16 bytes for transmission at one
time to this address if the FIFO is enabled by the application. If the FIFO is dis-
abled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and
UARTx_BRG_L registers. See Table 96.
Table 96. UART Transmit Holding Registers
(UART0_THR = 00C0h, UART1_THR = 00D0h)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
TxD
Value
00h–
FFh
Description
Transmit data byte.
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter