EZ80F91MCU Datasheet, PDF (263/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
244
EMAC Interrupts
Eight different sources of interrupts from the EMAC are described in Table 133.
Table 133. EMAC Interrupts
Interrupt
EMAC System Interrupts
Transmit State Machine Error
MIIMGT Done
Receive Overrun
EMAC Transmitter Interrupts
Transmit Control Frame
Transmit Done
EMAC Receiver Interrupts
Receive Control Frame
Receive Pause Control Frame
Receive Done
Description
Bit 7 (TxFSMERR_STAT) of the EMAC Interrupt Status Register
(EMAC_ISTAT). A Transmit State Machine Error should never
occur. However, if this bit is set, the entire transmitter module
must be reset.
Bit 6 (MGTDONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). This bit is set when communicating to the PHY
over the MII during a Read or Write operation.
Bit 2 (Rx_OVR_STAT) of the Interrupt Status Register
(EMAC_ISTAT). If this bit is set, all incoming packets are ignored
until this bit is cleared by software.
Transmit Control Frame = Bit 1 (Tx_CF_STAT) of the Interrupt
Status Register (EMAC_ISTAT). Denotes when control frame
transmission is complete.
Bit 0 (Tx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet transmission is complete.
Bit 5 (Rx_CF_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when control frame reception is
complete.
Bit 4 (Rx_PCF_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when pause control frame reception is
complete.
Bit 3 (Rx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when control frame reception is
complete.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller