EZ80F91MCU Datasheet, PDF (258/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
239
frequency at which the I²C bus is sampled must be at least 10 times the frequency
of the fastest master on the bus to ensure that START and STOP conditions are
always detected. By using two programmable clock divider stages, a high sam-
pling frequency can be ensured while allowing the MASTER mode output to be
set to a lower frequency.
Bus Clock Speed
The I²C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST
mode).
To ensure correct detection of START and STOP conditions on the bus, the I²C
must sample the I²C bus at least ten times faster than the bus clock speed of the
fastest master on the bus. The sampling frequency should therefore be at least
1 MHz (4 MHz in FAST mode) to guarantee correct operation with other bus mas-
ters.
The I²C sampling frequency is determined by the frequency of the eZ80F91 sys-
tem clock and the value in the I2C_CCR bits 2 to 0. The bus clock speed gener-
ated by the I²C in MASTER mode is determined by the frequency of the input
clock and the values in I2C_CCR[2:0] and I2C_CCR[6:3].
I²C Software Reset Register
The I2C_SRR register is a Write Only register. Writing any value to this register
performs a software reset of the I²C module. See Table 131.
Table 131. I²C Software Reset Register
(I2C_SRR = 00CDh)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
SRR
Value Description
00h– Writing any value to this register performs a software reset of
FFh the I²C module.
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface