EZ80F91MCU Datasheet, PDF (200/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
181
Real-Time Clock Control Register
This register contains control and status bits for the Real-Time Clock. Some bits in
the RTC_CTRL register are cleared by a RESET. The ALARM bit flag and associ-
ated interrupt (if INT_EN is enabled) are cleared by reading this register. The
ALARM bit flag is updated by clearing (locking) the RTC_UNLOCK bit or by an
increment of the RTC count. Writing to the RTC_CTRL register also resets the
RTC count prescaler allowing the RTC to be synchronized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from
SLEEP mode. This bit can be checked after RESET to determine if a sleep-mode
recovery is caused by the RTC. SLP_WAKE is cleared by a Read of the
RTC_CTRL register.
Setting the BCD_EN bit causes the RTC to use BCD counting in all registers
including the alarm set points.
The CLK_SEL and FREQ_SEL bits select the RTC clock source. If the 32 KHz
crystal option is selected the oscillator is enabled and the internal prescaler is set
to divide by 32768. If the power-line frequency option is selected, the prescale
value is set by the FREQ_SEL bit, and the 32 Khz oscillator is disabled. See Table
93.
Table 93. Real-Time Clock Control Register
(RTC_CTRL = 00EDh)
Bit
7
6
5
4
3
2
1
0
Reset
X
0
X
X
X
X
0/1
0
CPU Access
R R/W R/W R/W R/W R/W R R/W
Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write.
Bit
Position
7
ALARM
6
INT_EN
5
BCD_EN
Value Description
0
Alarm interrupt is inactive.
1
Alarm interrupt is active.
0
Interrupt on alarm condition is disabled.
1
Interrupt on alarm condition is enabled.
0
RTC count and alarm value registers are binary.
1
RTC count and alarm value registers are binary-coded
decimal (BCD).
PS019209-0504
PRELIMINARY
Real-Time Clock