EZ80F91MCU Datasheet, PDF (80/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
61
GPIO Register
Data (Input)
QD
QD
System Clock
Mode 1
Mode 4
Data Bus D Q
System Clock
GPIO Register
Data (Output)
Mode 1
Mode 3
Figure 5. GPIO Port Pin Block Diagram
V_DD
Port
Pin
GND
GPIO Interrupts
Each port pin can be used as an interrupt source. Interrupts can be either level- or
edge-triggered.
Level-Triggered Interrupts
When the port is configured for level-triggered interrupts, the corresponding port
pin is tristated. An interrupt request is generated when the level at the pin is the
same as the level stored in the Port x Data register. The port pin value is sampled
by the system clock. The input pin must be held at the selected interrupt level for a
minimum of 2 clock periods to initiate an interrupt. The interrupt request remains
active as long as this condition is maintained at the external source.
For example, if PA3 is programmed for low-level interrupt and the pin is forced
Low for 2 clock cycles, an interrupt request signal is generated from that port pin
and sent to the CPU. The interrupt request signal remains active until the external
device driving PA3 forces the pin High. The CPU must be enabled to respond to
interrupts for the interrupt request signal to be acted upon.
PS019209-0504
PRELIMINARY
General-Purpose Input/Output