EZ80F91MCU Datasheet, PDF (160/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
141
Timer Interrupt Identification Register
The TImer x Interrupt Identification Register, detailed in Table 56, is used to flag
timer events so that the CPU can determine the cause of a timer interrupt. This
register is cleared by a CPU Read.
Table 56. Timer Interrupt Identification Register
(TMR0_IIR = 0062h, TMR1_IIR = 0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h)
Bit
Reset
CPU Access
Note: R = Read only;
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
7
6
OC3
5
OC3
4
OC1
3
OC0
2
ICB
1
ICA
0
EOC
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Unused.
Output compare, OC3, does not occur.
Output compare, OC3, occurs.
Output compare, OC2, does not occur.
Output compare, OC2, occurs.
Output compare, OC1, does not occur.
Output compare, OC1, occurs.
Output compare, OC0, does not occur.
Output compare, OC0, occurs.
Input capture, ICB, does not occur.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICB, occurs.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICA, or PWM power trip does not occur.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
Input capture, ICA, or PWM power trip occurs.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
End-of-count does not occur.
End-of-count occurs.
PS019209-0504
PRELIMINARY
Programmable Reload Timers