EZ80F91MCU Datasheet, PDF (214/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
195
UART FIFO Control Register
This register is used to monitor trigger levels, clear FIFO pointers, and enable or
disable the FIFO. The UARTx_FCTL registers share the same I/O addresses as
the UARTx_IIR registers. See Table 101.
Table 101. UART FIFO Control Registers
(UART0_FCTL = 00C2h, UART1_FCTL = 00D2h)
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Bit
Position
[7:6]
TRIG
[5:3]
2
CLRTxF
1
CLRRxF
0
FIFOEN
Value
00
01
10
11
000b
0
1
0
1
0
1
Description
Receive FIFO trigger level set to 1. Receive data interrupt is
generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
Receive FIFO trigger level set to 4. Receive data interrupt is
generated when there are 4bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 8. Receive data interrupt is
generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 14. Receive data interrupt is
generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
Reserved—must be 000b.
No effect.
Clear the transmit FIFO and reset the transmit FIFO pointer.
Valid only if the FIFO is enabled.
No effect.
Clear the receive FIFO, clear the receive error FIFO, and
reset the receive FIFO pointer. Valid only if the FIFO is
enabled.
Transmit and receive FIFOs are disabled. Transmit and
receive buffers are only 1 byte deep.
Transmit and receive FIFOs are enabled. Note: Receive FIFO
will not be enabled during Multidrop Mode.
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter