EZ80F91MCU Datasheet, PDF (340/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
321
Each of these blocks is described in this overview section.
Phase Frequency Detector
The Phase Frequency Detector (PFD) is a digital block. The 2 inputs are the refer-
ence clock (XTAL oscillator; see the On-Chip Oscillators section on page 342)
and the PLL divider output. The 2 outputs drive the internal charge pump and rep-
resent the error (or difference) between the falling edges of the PFD inputs.
Charge Pump
The Charge Pump is an analog block that is driven by 2 digital inputs from the
PFD that control its programmable current sources. The internal current source
contains four programmable values: 1.5 mA, 1 mA, 500 µA, and 100 µA. These val-
ues are selected by PLL_CTRL1[7:6]. The selected current drive is sinked/
sourced onto the loop-filter node according to the error (or difference) between
the falling edges of the PFD inputs. Ideally, when the PLL is locked, there are no
errors (error = 0) and no current is sourced/sinked onto the loop-filter node.
Voltage Controlled Oscillator
The Voltage Controlled Oscillator is an analog block that exhibits an output fre-
quency proportional to its input voltage. The VCO input is driven from the charge
pump and filtered via the off-chip loop filter.
Loop Filter
The Loop Filter comprises off-chip passive components (usually 1 resistor and 2
capacitors) that filter/integrate charge from the internal charge pump. The filtered
node also drives the VCO input, which creates a proportional frequency output.
When the PLL is not used, the Loop Filter pin should be a No Connect.
Divider
The Divider is a digital, programmable downcounter. The divider input is driven by
the VCO. The divider output drives the PFD. The function of the Divider is to
divide the frequency of its input signal by a programmable factor N and supply the
result in its output.
MUX/CLK Sync
The MUX/CLK Sync is a digital, software-controllable multiplexer that selects
between PLL or the XTAL oscillator as the system clock (SCLK). A PLL source
can only be selected after the PLL is locked (via the lock detect block) to allow
glitch-free clock switching.
PS019209-0504
PRELIMINARY
Phase-Locked Loop