EZ80F91MCU Datasheet, PDF (33/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
14
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP BGA
Pin # Pin#
Symbol
Function
Signal Direction
Description
50 L5
MREQ
Memory
Request
Bidirectional, Active
Low
MREQ Low indicates that the
CPU is accessing a location in
memory. The RD, WR, and
INSTRD signals indicate the type
of access. The eZ80F91 device
does not drive this line during
RESET. It is an input in bus
acknowledge cycles.
51 K5
RD
Read
Output, Active Low
RD Low indicates that the
eZ80F91 device is reading from
the current address location. This
pin is tristated during bus
acknowledge cycles.
52 J5
WR
Write
Output, Active Low
WR indicates that the CPU is
writing to the current address
location. This pin is tristated
during bus acknowledge cycles.
53 M6
INSTRD
Instruction Output, Active Low
Read Indicator
INSTRD (with MREQ and RD)
indicates the eZ80F91 device is
fetching an instruction from
memory. This pin is tristated
during bus acknowledge cycles.
54 L6
WAIT
WAIT Request Schmitt-trigger input, Driving the WAIT pin Low forces
Active Low
the CPU to wait additional clock
cycles for an external peripheral
or external memory to complete
its Read or Write operation.
55 K6
RESET
Reset
Schmitt-trigger input, This signal is used to initialize the
Active Low
eZ80F91 device. This input must
be Low for a minimum of 3
system clock cycles, and must be
held Low until the clock is stable.
This input includes a Schmitt
trigger to allow RC rise times.
Note: *PHY represents the physical layer of the OSI model.
PS019209-0504
PRELIMINARY
Architectural Overview