EZ80F91MCU Datasheet, PDF (70/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
51
Reset
Reset Operation
The Reset controller within the eZ80F91 device features a consistent reset func-
tion for all types of resets that can affect the system. A system reset, referred to in
this document as RESET, returns the eZ80F91 to a defined state. All internal reg-
isters affected by a RESET return to their default conditions. RESET configures
the GPIO port pins as inputs and clears the CPU’s Program Counter to 000000h.
Program code execution ceases during RESET.
The events that can cause a RESET are:
• Power-On Reset (POR)
• Low-voltage brown-out (VBO)
• External RESET pin assertion
• Watch-Dog Timer (WDT) time-out when configured to generate a RESET
• Real-Time Clock alarm with the CPU in low-power SLEEP mode
• Execution of a Debug RESET command
Note:
During RESET, an internal RESET mode timer holds the system in RESET for
1025 system clock (SCLK) cycles to allow sufficient time for the primary crystal
oscillator to stabilize. For internal RESET sources, the RESET mode timer begins
incrementing on the next rising edge of SCLK following deactivation of the signal
that is initiating the RESET event. For external RESET pin assertion, the RESET
mode timer begins on the next rising edge of SCLK following assertion of the
RESET pin for three consecutive SCLK cycles.
The default clock source for SCLK on RESET is the crystal input (X_IN). Refer to
the CLK_MUX values in the PLL Control Register 0, Table 207 on page 325.
External Reset Input and Indicator
The eZ80F91 RESET pin functions as both an open-drain (active Low) RESET
mode indicator and as an active Low RESET input. When a RESET event occurs,
the internal circuitry begins driving the RESET pin Low. The RESET pin is held
Low by the internal circuitry until the internal RESET mode timer times out. If the
external reset signal is released prior to the end of the 1025-count time-out, pro-
gram execution begins following the RESET mode time-out. If the external reset
signal is released after the end of the 1025 count time-out, then program execu-
tion begins following release of the RESET input (the RESET pin is High for four
consecutive SCLK cycles).
PS019209-0504
PRELIMINARY
Reset