EZ80F91MCU Datasheet, PDF (142/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
123
Watch-Dog Timer Operation
Enabling and Disabling the WDT
The Watch-Dog Timer is disabled upon a RESET. To enable the WDT, the applica-
tion program must set WDT_EN, which corresponds to bit 7 of the WDT_CTL reg-
ister. After WDT_EN is set, no Writes are allowed to the WDT_CTL register. When
enabled, the WDT cannot be disabled, except by a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—2¹⁸, 2²², 2²⁵, and 2²⁷
timer clock cycles. The WDT time-out period is defined by the WDT_PERIOD field
of the WDT_CTL register (WDT_CTL[1:0]). The approximate time-out periods for
two different WDT clock sources are listed in Table 46. The approximate time-out
period for the third WDT clock source is listed in Table 47.
Table 46. Watch-Dog Timer Approximate Time-Out Delays
Clock Source
32.768 KHz Crystal Oscillator
32.768 KHz Crystal Oscillator
32.768 KHz Crystal Oscillator
32.768 KHz Crystal Oscillator
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
Divider
Value
2¹⁸
2²²
2²⁵
2²⁷
2¹⁸
2²²
2²⁵
2²⁷
Time Out
Delay
8.00 s
128 s
1024 s
4096 s
5.2 ms
83.9 ms
0.67 s
2.68 s
Table 47. Watch-Dog Timer Approximate Time-Out Delays w/ Internal RC Oscillator
Clock Source
Internal RC Oscillator
Internal RC Oscillator
Internal RC Oscillator
Internal RC Oscillator
Divider
Value
2¹⁸
2²²
2²⁵
2²⁷
Minimum
Typical
Time-Out Delay Time-Out Delay
16s
26 s
262s
419s
2100 s
3360s
8390s
13400s
PS019209-0504
PRELIMINARY
Watch-Dog Timer