EZ80F91MCU Datasheet, PDF (277/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
258
EMAC Interpacket Gap
EMAC Interpacket Gap Overview
Interpacket gap (IPG) is measured between the last nibble of the frame check
sequence (FCS) and the first nibble of the preamble of the next packet. Three reg-
isters are available to fine tune the IPG, the EMAC_IPGT, EMAC_IPGR1, and the
EMAC_IPGR2. The first register EMAC_IPGT determines the back-to-back
Transmit IPG. The other two registers determine the non-back-to-back IPG in two
parts. Table 145 shows the values for the EMAC_IPGT and the corresponding
IPGs for both full-duplex and half-duplex modes.
Table 145. EMAC_IPGT Back-to-Back Settings for Full/Half Duplex Modes*
MII, RMII/SMII, PMD
(100 Mbps)
MII, RMII/SMII
(10 Mbps)
ENDEC Mode
(10 Mbps)
Clock Period = 40 nsec
IPGT[6:0]
Clock Period = 400 nsec
IPGT[6:0]
Clock Period = 100 nsec
IPGT[6:0]
Half
Full Interpacket Half
Full Interpacket Half
Full Interpacket
Duplex Duplex
Gap
Duplex Duplex
Gap
Duplex Duplex
Gap
0Dh
0.12 µs
00h
1.2 µs
10h
1.9 µs
0Bh
0.44 µs
08h
4.4 µs
18h
2.7 µs
0Ch
0.60 µs
0Ch
6.0 µs
20h
3.5 µs
10h
0.76 µs
10h
7.5 µs
40h
6.7 µs
12h
15h
0.96 µs
12h
15h
9.6 µs
5Ah
5Dh
9.6 µs
20h
1.40 µs
20h
14.0 µs
20h
13.0 µs
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
The equations for back-to-back Transmit IPG are determined by the following:
Full Duplex Mode (3 clocks + IPGT clocks) * clock period = IPG
Half Duplex Mode (6 clocks + IPGT clocks) * clock period = IPG
Table 146 shows the IPGR2 settings for the non-back-to-back packets.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller