EZ80F91MCU Datasheet, PDF (73/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
54
Low Power Modes
Overview
The eZ80F91 device provides a range of power-saving features. The highest level
of power reduction is provided by SLEEP mode. The next level of power reduction
is provided by the HALT instruction. The most basic level of power reduction is
provided by the clock peripheral power-down registers.
SLEEP Mode
Execution of the CPU’s SLP instruction places the eZ80F91 device into SLEEP
mode. In SLEEP mode, the operating characteristics are:
• The primary crystal oscillator is disabled
• The system clock is disabled
• The CPU is idle
• The Program Counter (PC) stops incrementing
• The 32KHz crystal oscillator continues to operate and drive the Real-Time
Clock and the Watch-Dog Timer (if WDT is configured to operate from the
32 KHz oscillator)
The CPU can be brought out of SLEEP mode by any of the following operations:
• A RESET via the external RESET pin driven Low
• A RESET via a Real-Time Clock alarm
• A RESET via a Watch-Dog Timer time-out (if running off of the 32KHz oscilla-
tor and configured to generate a RESET upon time-out)
• A RESET via execution of a Debug RESET command
After exiting SLEEP mode, the standard RESET delay occurs to allow the primary
crystal oscillator to stabilize. Refer to the Reset section on page 51 for more infor-
mation.
HALT Mode
Execution of the CPU’s HALT instruction places the eZ80F91 device into HALT
mode. In HALT mode, the operating characteristics are:
• The primary crystal oscillator is enabled and continues to operate
PS019209-0504
PRELIMINARY
Low Power Modes