EZ80F91MCU Datasheet, PDF (52/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
33
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP BGA
Pin # Pin#
Symbol
Function
Signal Direction
Description
141 C4
RxD3
MII Receive Input
Data
This pin is used by the Ethernet
MAC for the MII Interface to the
PHY. Receive Data is provided
by the MII PHY Interface
synchronous to the rising-edge of
Rx_CLK.
142 A3
MDC
MII
Output
Management
Data Clock
This pin is used by the Ethernet
MAC for the MII Management
Interface to the PHY. The
Ethernet MAC provides the MII
Management Data Clock to the
MII PHY Interface.
143 B3
MDIO
MII
Bidirectional
Management
Data
This pin is used by the Ethernet
MAC for the MII Management
Interface to the PHY. The
Ethernet MAC sends and
receives the MII Management
Data to and from the MII PHY
Interface.
144 A2
WP
Write Protect
Schmitt-trigger input, The Write Protect input is used by
Active Low
the Flash Controller to protect the
Boot Block from Write and
ERASE operations.
Note: *PHY represents the physical layer of the OSI model.
System Clock Source Options
System Clock. The eZ80F91 device’s internal clock, SCLK, is responsible for
clocking all internal logic. The SCLK source can be an external crystal oscillator,
an internal PLL, or an internal 32 kHz RTC oscillator. The SCLK source is selected
by PLL Control Register 0. RESET default is provided by the external crystal oscil-
lator. Refer to the CLK_MUX values in the PLL Control Register 0, Table 207 on
page 325 for details.
PHI. PHI is a device output driven by SCLK that can be used for system synchro-
nization to the eZ80F91 device. PHI is used as the reference clock for all AC
Characteristics.
External Crystal Oscillator. An externally-driven oscillator that can operate in two
modes. In one mode, the X_IN pin can be driven by a can oscillator from DC up to
PS019209-0504
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