EZ80F91MCU Datasheet, PDF (335/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
316
Table 204. Pin to Boundary Scan Cell Mapping (Continued)
Pin
Direction Scan Cell # Pin
Direction Scan Cell #
CS2
Output
36
PB7
OEN
143
CS1
Output
37
PB6
Input
144
CS0
Output
38
PB6
Output
145
A23
Input
39
PB6
OEN
146
A23
Output
40
PB5
Input
147
A22
Input
41
PB5
Output
148
A22
Output
42
PB5
OEN
149
A21
Input
43
PB4
Input
150
A21
Output
44
PB4
Output
151
A20
Input
45
PB4
OEN
152
A20
Output
46
PB3
Input
153
A19
Input
47
PB3
Output
154
A19
Output
48
PB3
OEN
155
A18
Input
49
PB2
Input
156
A18
Output
50
PB2
Output
157
A17
Input
51
PB2
OEN
158
A17
Output
52
PB1
Input
159
A16
Input
53
PB1
Output
160
A16
Output
54
PB1
OEN
161
A16
OEN
55
PB0
Input
162
A15
Input
56
PB0
Output
163
A15
Output
57
PB0
OEN
164
A14
Input
58
PC7
Input
165
A14
Output
59
PC7
Output
166
A13
Input
60
PC7
OEN
167
Notes:
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
shown to be associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated
with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
PS019209-0504
PRELIMINARY
On-Chip Instrumentation