EZ80F91MCU Datasheet, PDF (118/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
99
Normal bus operation of the eZ80F91 device using CS0 to communicate to an
external peripheral is shown in Figure 19. Figure 20 shows an external bus mas-
ter communicating with an external peripheral during bus acknowledge cycles.
eZ80F91 MCU
WAIT
RD
WR
DATA
ADDRESS
External
Peripheral
IORQ
MREQ
eZ80F91
Chip Select
Wait State
Generator
CS0
CS1
CS2
CS3
Figure 19. Memory Interface Bus Operation During CPU Bus Cycles, Normal Operation
External
Master
WAIT
RD
WR
DATA
ADDRESS
External
Peripheral
IORQ
MREQ
eZ80F91
Chip Select
Wait State
Generator
CS0
CS1
CS2
CS3
Figure 20. Memory Interface Bus Operation During Bus Acknowledge Cycles
PS019209-0504
PRELIMINARY
Bus Arbiter