EZ80F91MCU Datasheet, PDF (339/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
320
Phase-Locked Loop
Overview
The Phase-Locked-Loop (PLL) is a programmable frequency multiplier that satis-
fies the equation SCLK (Hz) = N * F_OSC(Hz). A diagram of the PLL block is shown
in Figure 60.
System Clock
(F_OSC < SCLK < F_OSC* N)
SCLK-MUX
PLL_CTL1[0] = PLL Enable
(1MHz < F_OSC< 10MHz)
x2
x1 ^Oscillator
RTC_CLK
PFD
Charge
Pump
VCO
PLL_INT
Lock ^{PLL_CTL0[7:6]}
Detect
Div N
PLL_CTL0[3:2]
{PLL_DIV_H, PLL_DIV_L}
Figure 60. Phase-Locked Loop Block Diagram
The seven main blocks of the PLL are:
• Phase Frequency Detector
• Charge Pump
• Voltage Controlled Oscillator
• Loop Filter
• Divider
• MUX/CLK Sync
• Lock Detect
Off-Chip
Loop Filter
C_PLL1
R_PLL
C_PLL2
PS019209-0504
PRELIMINARY
Phase-Locked Loop