EZ80F91MCU Datasheet, PDF (336/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
317
Table 204. Pin to Boundary Scan Cell Mapping (Continued)
Pin
Direction Scan Cell # Pin
Direction Scan Cell #
A13
Output
61
PC6
Input
168
A12
Input
62
PC6
Output
169
A12
Output
63
PC6
OEN
170
A11
Input
64
PC5
Input
171
A11
Output
65
PC5
Output
172
A10
Input
66
PC5
OEN
173
A10
Output
67
PC4
Input
174
A9
Input
68
PC4
Output
175
A9
Output
69
PC4
OEN
176
A8
Input
70
PC3
Input
177
A8
Output
71
PC3
Output
178
A8
OEN
72
PC3
OEN
179
A7
Input
73
PC2
Input
180
A7
Output
74
PC2
Output
181
A6
Input
75
PC2
OEN
182
A6
Output
76
PC1
Input
183
A5
Input
77
PC1
Output
184
A5
Output
78
PC1
OEN
185
A4
Input
79
PC0
Input
186
A4
Output
80
PC0
Output
187
A3
Input
81
PC0
OEN
188
A3
Output
82
PD7
Input
189
A2
Input
83
PD7
Output
190
A2
Output
84
PD7
OEN
191
A1
Input
85
PD6
Input
192
Notes:
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
shown to be associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated
with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
PS019209-0504
PRELIMINARY
On-Chip Instrumentation