EZ80F91MCU Datasheet, PDF (59/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
40
Table 3. Register Map (Continued)
Address
(hex) Mnemonic
Name
Reset
CPU Page
(hex) Access #
Timers and PWM, continued
0069 TMR1_DR_H
Timer 1 Data Register—High Byte
XX
R
143
TMR1_RR_H
Timer 1 Reload Register—High Byte
XX
W
144
006A TMR1_CAP_CTL Timer 1 Input Capture Control Register XX
R/W 144
006B TMR1_CAPA_L
Timer 1 Capture Value A Register—
XX
R/W 145
Low Byte
006C TMR1_CAPA_H
Timer 1 Capture Value A Register—
XX
R/W 146
High Byte
006D TMR1_CAPB_L
Timer 1 Capture Value B Register—
XX
R/W 146
Low Byte
006E TMR1_CAPB_H
Timer 1 Capture Value B Register—
XX
R/W 147
High Byte
006F TMR2_CTL
Timer 2 Control Register
00
R/W 138
0070 TMR2_IER
Timer 2 Interrupt Enable Register
00
R/W 139
0071 TMR2_IIR
Timer 2 Interrupt Identification Register 00
R/W 141
0072 TMR2_DR_L
Timer 2 Data Register—Low Byte
XX
R
142
TMR2_RR_L
Timer 2 Reload Register—Low Byte
XX
W
143
0073 TMR2_DR_H
Timer 2 Data Register—High Byte
XX
R
143
TMR2_RR_H
Timer 2 Reload Register—High Byte
XX
W
144
0074 TMR3_CTL
Timer 3 Control Register
00
R/W 138
0075 TMR3_IER
Timer 3 Interrupt Enable Register
00
R/W 139
0076 TMR3_IIR
Timer 3 Interrupt Identification Register 00
R/W 141
0077 TMR3_DR_L
Timer 3 Data Register—Low Byte
XX
R
142
TMR3_RR_L
Timer 3 Reload Register—Low Byte
XX
W
143
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
out reset, the Watch-Dog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read Only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a
an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.
5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
PS019209-0504
PRELIMINARY
Register Map