EZ80F91MCU Datasheet, PDF (112/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
93
Chip Select Registers
Chip Select x Lower Bound Register
For Memory Chip Selects, the Chip Select x Lower Bound register, detailed in
Table 26, defines the lower bound of the address range for which the correspond-
ing Memory Chip Select (if enabled) can be active. For I/O Chip Selects, this reg-
ister defines the address to which ADDR[15:8] is compared to generate an I/O
Chip Select. All Chip Select lower bound registers reset to 00h.
Table 26. Chip Select x Lower Bound Register
(CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h)
Bit
7
6
5
4
3
2
1
0
CS0_LBR Reset
0
0
0
0
0
0
0
0
CS1_LBR Reset
0
0
0
0
0
0
0
0
CS2_LBR Reset
0
0
0
0
0
0
0
0
CS3_LBR Reset
0
0
0
0
0
0
0
0
CPU Access
R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSX_LBR
Value Description
00h–
FFh
For Memory Chip Selects (CSx_IO = 0)
This byte specifies the lower bound of the Chip Select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a Memory Chip Select signal should be
generated.
For I/O Chip Selects (CSx_IO = 1)
This byte specifies the Chip Select address value. ADDR[15:8] is
compared to the values contained in these registers for
determining whether an I/O Chip Select signal should be
generated.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States