EZ80F91MCU Datasheet, PDF (311/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
292
ZDI Data Bytes
ZCL
7
8
9
1
2
3
7
8
9
1
2
9
ZDA
A0 Write 0/1 D7 D6 D5 D1 D0 0/1
D7
D6 1
msb
of DATA
Byte 1
lsb
of DATA
Byte 1
msb
of DATA
Byte 2
lsb of
Single-Bit
ZDI Address Byte Separator
Single-Bit
Byte Separator
Figure 57. ZDI Block Data Write Timing
ZDI Read Operations
ZDI Single-Byte Read
Single-byte Read operations are initiated in the same manner as single-byte Write
operations, with the exception that the R/W bit of the ZDI register address is set to
1. Upon receipt of a slave address with the R/W bit set to 1, the eZ80F91 device’s
ZDI block loads the selected data into the shifter at the beginning of the first cycle
following the single-bit data separator. The most-significant bit (msb) is shifted out
first. Figure 58 illustrates the timing for ZDI single-byte Read operations.
ZDI Data Byte
ZCL
7
8
9
1
2
3
4
5
6
7
8
9
ZDA
A0 Read 0/1 D7 D6 D5 D4
msb
of DATA
lsb of
Single-Bit
ZDI Address Byte Separator
Figure 58. ZDI Single-Byte Data Read Timing
D3 D2
D1
D0 1
lsb
of DATA
End of Data
or New ZDI
START Signal
ZDI Block Read
A block Read operation is initiated in the same manner as a single-byte Read;
however, the ZDI master continues to clock in the next byte from the ZDI slave as
the ZDI slave continues to output data. The ZDI register address counter incre-
PS019209-0504
PRELIMINARY
ZiLOG Debug Interface