EZ80F91MCU Datasheet, PDF (234/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
215
SPI Baud Rate Generator Registers—Low Byte and High Byte
These registers hold the Low and High bytes of the 16-bit divisor count loaded by
the CPU for baud rate generation. The 16-bit clock divisor value is returned by
{SPI_BRG_H, SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to
0002h. When configured as a Master, the 16-bit divisor value must be between
0003h and FFFFh, inclusive. When configured as a Slave, the 16-bit divisor value
must be between 0004h and FFFFh, inclusive.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes
both bytes to be loaded into the BRG counter and a restart of the count. See
Tables 112 and 113.
Table 112. SPI Baud Rate Generator Register—Low Byte
(SPI_BRG_L = 00B8h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
Bit
Position
[7:0]
SPI_BRG_L
Value
00h–
FFh
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
Table 113. SPI Baud Rate Generator Register—High Byte
(SPI_BRG_H = 00B9h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:0]
SPI_BRG_H
Value
00h–
FFh
Description
These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
PS019209-0504
PRELIMINARY
Serial Peripheral Interface