EZ80F91MCU Datasheet, PDF (278/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
259
Table 146. EMAC_IPGT Non-Back-to-Back Settings for Full/Half Duplex Modes*
MII, RMII/SMII, PMD
(100 Mbps)
MII, RMII/SMII
(10 Mbps)
Clock Period = 40 nsec Clock Period = 400 nsec
IPGR2[6:0] Interpacket IPGR2[6:0] Interpacket
Gap
Gap
00h
0.24 µs
00h
2.4 µs
10h
0.88 µs
10h
8.8 µs
12h
0.96 µs
12h
9.6 µs
20h
1.52 µs
20h
15.2 µs
40h
2.80 µs
40h
28.0 µs
7Fh
5.32 µs
7Fh
53.2 µs
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
ENDEC Mode
(10 Mbps)
Clock Period = 100 nsec
IPGR2[6:0] Interpacket
Gap
00h
0.6 µs
10h
2.2 µs
20h
3.8 µs
40h
7.0 µs
5Ah
9.6 µs
7Fh
13.3 µs
A non-back-to-back Transmit IPG is determined by the following formula:
(6 clocks + IPGR2 clocks) * clock period = IPG
The difference in values between Tables 145 and 146 is due to the asynchronous
nature of the Carrier Sense (CRS). The CRS must undergo a 2-clock synchroni-
zation before the internal Tx state machine can detect it. This synchronization
equates to a 6-clock intrinsic delay between packets instead of the 3-clock intrin-
sic delay in the back-to-back packet mode. More information covering this topic
can be found in the IEEE 802.3/4.2.3.2.1 Carrier Deference section.
EMAC Interpacket Gap Register
The EMAC Interpacket Gap is a programmable field representing the interpacket
gap (IPG) between back-to-back packets. It is the IPG parameter used in full-
duplex and half-duplex modes between back-to-back packets. Set this field to the
appropriate number of IPG octets. The default setting of 15h represents the mini-
mum IPG of 0.96 µs (at 100 Mbps) or 9.6 µs (at 10Mbps). See Table 147.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller