EZ80F91MCU Datasheet, PDF (206/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
187
An interrupt due to one of the above conditions is cleared when the UARTx_LSR
register is read. In case of FIFO mode, a line status interrupt is generated only
after the received byte with an error reaches the top of the FIFO and is ready to be
read.
A line status interrupt is activated (provided this interrupt is enabled) as long as
the Read pointer of the receiver FIFO points to the location of the FIFO that con-
tains a byte with the error. The interrupt is immediately cleared when the
UARTx_LSR register is read. The ERR bit of the UARTx_LSR register is active as
long as an erroneous byte is present in the receiver FIFO.
UART Modem Status Interrupt
The modem status interrupt is generated if there is any change in state of the
modem status inputs to the UART. This interrupt is cleared when the CPU reads
the UARTx_MSR register.
UART Recommended Usage
The following standard sequence of events occurs in the UART block of the
eZ80F91 device. A description of each follows.
1. Module reset.
2. Control transfers to configure UART operation.
3. Data transfers.
Module Reset
Upon reset, all internal registers are set to their default values. All command sta-
tus registers are programmed with their default values, and the FIFOs are flushed.
Control Transfers
Based on the requirements of the application, the data transfer baud rate is deter-
mined and the BRG is configured to generate a 16X clock frequency. Interrupts
are disabled and the communication control parameters are programmed in the
UARTx_LCTL register. The FIFO configuration is determined and the receive trig-
ger levels are set in the UARTx_FCTL register. The status registers, UARTx_LSR
and UARTx_MSR, are read to ensure that none of the interrupt sources are
active. The interrupts are enabled (except for the transmit interrupt) and the appli-
cation is ready to use the module for transmission/reception.
Data Transfers
Transmit. To transmit data, the application enables the transmit interrupt. An inter-
rupt is immediately expected in response. The application reads the UARTx_IIR
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter