EZ80F91MCU Datasheet, PDF (343/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
324
The divider is designed such that any divider value less than 2 is ignored; a value
of 2 is used in its place.
The least-significant byte of PLL divider N is set via the corresponding bits in the
PLL_DIV_L register. See Tables 205 and 206.
Note: The PLL divider register can only be written to when the PLL is disabled. A read-
back of the PLL Divider registers returns 0.
Table 205. PLL Divider Register—Low Bytes
(PLL_DIV_L = 005Ch)
Bit
Reset
CPU Access
Note: W = Write only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
PLL_DIV_L
Value
00h–
FFh
Description
These bits represent the Low byte of the 11-bit PLL divider
value. The complete PLL divider value is returned by
{PLL_DIV_H, PLL_DIV_L}.
Table 206. PLL Divider Register—High Bytes
(PLL_DIV_H = 005Dh)
Bit
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
CPU Access
W
W
W
W
W
W
W
W
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:3]
[2:0]
PLL_DIV_H
Value
00h
0h–7h
Description
Reserved
These bits represent the High byte of the 11-bit PLL divider
value. The complete PLL divider value is returned by
{PLL_DIV_H, PLL_DIV_L}.
PS019209-0504
PRELIMINARY
Phase-Locked Loop