EZ80F91MCU Datasheet, PDF (264/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
245
EMAC Shared Memory Organization
Internal Ethernet SRAM shares memory with the CPU. This memory is divided
into the Transmit buffer and the Receive buffer by defining three registers, as
listed below.
• Transmit Lower Boundary Pointer (TLBP)—this register points to the start of
the Transmit buffer in the internal Ethernet shared memory space
• Boundary Pointer (BP)—this register points to the start of the Receive buffer
• Receive High Boundary Pointer (RHBP)—this register points to the end of the
Receive buffer + 1
This internal Ethernet shared memory is depicted in Figure 48.
TLBP
BP
RHBP
Tx Buffer
Rx Buffer
Figure 48. internal Ethernet Shared Memory
The Transmit and Receive buffers are able to be subdivided into packet buffers of
32, 64, 128, or 256 bytes in size. The packet buffer size is set in bits 7 and 6 of the
EmacBufSize register. An Ethernet packet can accommodate multiple packet buff-
ers. At the start of each packet is a descriptor table that describes the packet.
Each actual Ethernet packet follows the descriptor table, as illustrated in
Figure 49.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller