EZ80F91MCU Datasheet, PDF (294/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
275
Table 170. EMAC Buffer Size Register
(EMAC_BUFSZ = 004Bh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
Value Description
[7:6]
BUFSZ
00
Set EMAC Rx/Tx buffer size to 256 bytes.
01
Set EMAC Rx/Tx buffer size to 128 bytes.
10
Set EMAC Rx/Tx buffer size to 64 bytes.
11
Set EMAC Rx/Tx buffer size to 32 bytes.
[5:0]
TPCF_LEV
00h–
3Fh
Transmit Pause Control Frame level.*
Note: *00h disables the hardware-generated Transmit Pause Control Frame.
EMAC Interrupt Enable Register
Enabling the Receive Overrun interrupt allows software to detect an overrun con-
dition as soon as it occurs. If this interrupt is not set, then an overrun cannot be
detected until the software processes the Receive packet with the overrun and
checks the Receive status in the Rx descriptor table. Because the receiver is dis-
abled by an overrun error until the Rx_OVR bit is cleared in the EMAC_ISTAT reg-
ister, this packet is the final packet in the Receive buffer. To reenable the receiver
before all of the Receive packets are processed and the Receive buffer is empty,
software can enable this interrupt to detect the overrun condition early. As it pro-
cesses the Receive packets, it can reenable the receiver when the number of free
buffers is greater than the number of minimum buffers. See Table 171.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller