EZ80F91MCU Datasheet, PDF (125/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
106
Flash Memory Overview
The eZ80F91 device includes a Flash memory controller that automatically con-
verts standard CPU Read and Write cycles to the specific protocol required for the
Flash memory array. As such, standard memory Read and Write instructions
access the Flash memory array as if it is internal RAM. The controller also sup-
ports I/O access to the Flash memory array, in effect presenting it as an indirectly-
addressable bank of I/O registers. These access methods are also supported via
the ZDI and OCI interfaces.
In addition, eZ80Acclaim! Flash Microcontrollers support a Flash Read–While–
Write methodology. In essence, the eZ80^® CPU can continue to read and execute
code from an area of Flash memory while a nonconflicting area of Flash memory
is being programmed.
The Flash memory controller contains a frequency divider, a Flash register inter-
face, and a Flash control state machine. A simplified block diagram of the Flash
controller is illustrated in Figure 23.
System Clock
Clock Divider
8-bit downcounter
ADDR ¹⁷
eZ80 Core
Interface
D_{OUT 8}
Flash
Control
Registers
Figure 23. Flash Memory Block Diagram
FADDR
17
FD_IN
8
FCNTL
9
Flash
State ^MAIN_INFO
Machine
FD_OUT 8
Flash
256 KB
+
512 bytes
CPUD_OUT 8
FLASH_IRQ
Reading Flash Memory
The main Flash memory array can be read using both Memory and I/O opera-
tions. As an auxiliary storage area, the information page is only accessible via I/O
operations. In all cases, wait states are automatically inserted to allow for read
access time.
PS019209-0504
PRELIMINARY
Flash Memory