EZ80F91MCU Datasheet, PDF (249/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
230
Note: When I²C contains a 10-bit slave address (signified by the address range F0h–
F7h in the I2C_SAR register), it transmits an ACK when the first address byte is
received after a restart. An interrupt is generated and IFLG is set to 1; however,
the status does not change. No second address byte is sent by the master. It is up
to the slave to remember it had been selected prior to the restart.
I²C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is
lost during the transmission of an address, and the slave address and Read bit
are received. This action is represented by the status code B0h in the I2C_SR reg-
ister.
The data byte to be transmitted is loaded into the I2C_DR register and the IFLG bit
is cleared to 0. After the I²C transmits the byte and receives an ACK, the IFLG bit
is set to 1 and the I2C_SR register contains B8h. When the final byte to be trans-
mitted is loaded into the I2C_DR register, the AAK bit is cleared when the IFLG is
cleared to 0. After the final byte is transmitted, the IFLG is set and the I2C_SR reg-
ister contains C8h and the I²C returns to an idle state. The AAK bit must be set to
1 before reentering SLAVE mode.
If no ACK is received after transmitting a byte, the IFLG is set and the I2C_SR reg-
ister contains C0h. The I²C then returns to an idle state.
If a STOP condition is detected after an ACK bit, the I²C returns to an idle state.
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master
transmitter.
The I²C enters SLAVE RECEIVE mode when it receives its own slave address
and a Write bit (lsb = 0) after a START condition. The I²C transmits an ACK bit and
sets the IFLG bit in the I2C_CTL register and the I2C_SR register contains the sta-
tus code 60h. The I²C also enters SLAVE RECEIVE mode when it receives the
general call address 00h (if the GCE bit in the I2C_SAR register is set). The status
code is then 70h.
Note: When the I²C contains a 10-bit slave address (signified by F0h–F7h in the
I2C_SAR register), it transmits an acknowledge after the first address byte is
received but no interrupt is generated. IFLG is not set and the status does not
change. The I²C generates an interrupt only after the second address byte is
received. The I²C sets the IFLG bit and loads the status code as described above.
I²C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost
during the transmission of an address, and the slave address and Write bit (or the
general call address if the CGE bit in the I2C_SAR register is set to 1) are
received. The status code in the I2C_SR register is 68h if the slave address is
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface