EZ80F91MCU Datasheet, PDF (274/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
255
EMAC Configuration Register 4
The EMAC Configuration Register 4 controls pause control frame behavior, back
pressure, and receive frame acceptance. See Table 141.
Table 141. EMAC Configuration Register 4
(EMAC_CFG4 = 0024h)
Bit
7
6
Reset
0
0
CPU Access
R R/W
Note: R = Read Only; R/W = Read/Write.
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
7
6
TPCF
5
THDF
4
PARF
3
RxFC
2
TxFC
1
TPAUSE
0
RxEN
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Reserved.
Do not transmit a pause control frame.
Transmit pause control frame (full duplex mode). TPCF
continually sends pause control frames until negated.
Disable back pressure.
EMAC asserts back pressure on the link. Back pressure
causes preamble to be transmitted, raising carrier sense (half
duplex mode).
Only accept frames that meet preset criteria (i.e. address,
CRC, length, etc.).
All frames are received regardless of address, CRC, length,
etc.
EMAC ignores received pause control frames.
EMAC acts upon pause control frames received.
PAUSE control frames are NOT allowed to be transmitted.
PAUSE control frames are allowed to be transmitted.
Do not force a pause condition.
Force a pause condition while this bit is asserted.
Do not receive frames.
Allow Receive frames to be received.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller