EZ80F91MCU Datasheet, PDF (243/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
224
Special attention must be paid if, during a serial transfer, the arbitration procedure
is still in progress at the moment when a repeated START condition or a STOP
condition is transmitted to the I²C bus. If it is possible for such a situation to occur,
the masters involved must send this repeated START condition or STOP condition
at the same position in the format frame. In other words, arbitration is not allowed
between:
• A repeated START condition and a data bit
• A STOP condition and a data bit
• A repeated START condition and a STOP condition
Clock Synchronization for Handshake
The clock-synchronizing mechanism can function as a handshake, enabling
receivers to cope with fast data transfers, on either a byte or a bit level. The byte
level allows a device to receive a byte of data at a fast rate, but allows the device
more time to store the received byte or to prepare another byte for transmission.
Slaves hold the SCL line Low after reception and acknowledge the byte, forcing
the master into a wait state until the slave is ready for the next byte transfer in a
handshake procedure.
Operating Modes
Master Transmit
In MASTER TRANSMIT mode, the I²C transmits a number of bytes to a slave
receiver.
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register
to 1. The I²C then tests the I²C bus and transmits a START condition when the
bus is free. When a START condition is transmitted, the IFLG bit is 1 and the sta-
tus code in the I2C_SR register is 08h. Before this interrupt is serviced, the
I2C_DR register must be loaded with either a 7-bit slave address or the first part
of a 10-bit slave address, with the lsb cleared to 0 to specify TRANSMIT mode.
The IFLG bit should now be cleared to 0 to prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit
are transmitted, the IFLG is set again. A number of status codes are possible in
the I2C_SR register. See Table 118.
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface