EZ80F91MCU Datasheet, PDF (376/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
357
General Purpose I/O Port Input Sample Timing
Figure 70 illustrates timing of the GPIO input sampling. The input value on a GPIO
port pin is sampled on the rising edge of the system clock. The port value is then
available to the CPU on the second rising clock edge following the change of the
port value.
T_CLK
PHI
GPIO Pin
Input Value
Port Value
Changes to 0
GPIO Input
Data Latch
GPIO Data
READ on Data Bus
0 Latched
Into GPIO
Data Register
Figure 70. Port Input Sample Timing
GPIO Data Register
Value 0 Read
by eZ80
General Purpose I/O Port Output Timing
Figure 71 and Table 240 provide timing information for GPIO port pins.
T_CLK
PHI
Port Output
T₁
T₂
Figure 71. GPIO Port Output Timing
PS019209-0504
PRELIMINARY
Electrical Characteristics