EZ80F91MCU Datasheet, PDF (260/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
241
Note: MII PHY is a Physical Layer transceiver device; PHY does not refer to the
eZ80F91 system clock output pin, PHI.
The MII management module provides a two-wire control/status path to the MII .
Read and Write communication to and from registers within the PHY is accom-
plished via the host interface.
EMAC Functional Description
The EMAC block implements memory, arbiter, and transmit and receive direct
memory access functions, as described in this section.
Memory
EMAC memory is the shared Ethernet memory location of the Transmit and
Receive buffers. This memory is broken into two parts: the Tx buffer and the Rx
buffer. The Transmit Lower Boundary Pointer Register, EmacTLBP, is the register
that holds the starting address of the Tx buffer. The Boundary Pointer Register,
EmacBP, points to the start of the Rx buffer (end of Tx buffer + 1). The Receive
High Boundary Pointer Register, EmacRHBP, points to the end of the Rx buffer +
1. The Tx and Receive buffers are divided into packet buffers of either 256, 128,
64, or 32 bytes. These buffer sizes are selected by EmacBufSize register bits 7
and 6.
The EmacBlksLeft register contains the number of Receive packet buffers remain-
ing in the Rx buffer. This buffer can be used for software flow control. If the
Block_Level is nonzero (bits 5:0 of the EmacBufSize register), hardware flow con-
trol is enabled. If in Full Duplex Mode, the EMAC transmits a pause control frame
when the EmacBlksLeft register is less than the Block_Level. In Half Duplex
mode, the EMAC continually transmits a nibble pattern of hexadecimal 5’s to jam
the channel.
Four pointers are defined for reading and writing the Tx and Rx buffers. The
Transmit Write Pointer, TWP, is a software pointer that points to the next available
packet buffer. The TWP is reset to the value stored in EmacTLBP. The Transmit
Read Pointer, TRP, is a hardware pointer in the Transmit Direct Memory Access
Register, TxDMA, that contains the address of the next packet to be transmitted. It
is automatically reset to the EmacTLBP. The Receive Write Pointer, RWP, is a
hardware pointer in the Receive Direct Memory Access Register, RxDMA, which
contains the storage address of the incoming packet. The RWP pointer is auto-
matically initialized to the Boundary Pointer registers. The Receive Read Pointer,
RRP, is a software pointer to where the next packet should be read from. The
RRP pointer should be initialized to the Boundary Pointer registers. For the hard-
ware flow control to function properly, the software must update the hardware
RRP (EmacRrp) pointer whenever the software version is updated. The RxDMA
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller