EZ80F91MCU Datasheet, PDF (116/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
97
Bit
Position
Value Description
[3:0]
BUS_CYCLE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not valid.
Each bus mode state is 1 eZ80^® clock cycle in duration.^{1, 2, 3}
Each bus mode state is 2 eZ80^® clock cycles in duration.
Each bus mode state is 3 eZ80^® clock cycles in duration.
Each bus mode state is 4 eZ80^® clock cycles in duration.
Each bus mode state is 5 eZ80^® clock cycles in duration.
Each bus mode state is 6 eZ80^® clock cycles in duration.
Each bus mode state is 7 eZ80^® clock cycles in duration.
Each bus mode state is 8 eZ80^® clock cycles in duration.
Each bus mode state is 9 eZ80^® clock cycles in duration.
Each bus mode state is 10 eZ80^® clock cycles in duration.
Each bus mode state is 11 eZ80^® clock cycles in duration.
Each bus mode state is 12 eZ80^® clock cycles in duration.
Each bus mode state is 13 eZ80^® clock cycles in duration.
Each bus mode state is 14 eZ80^® clock cycles in duration.
Each bus mode state is 15 eZ80^® clock cycles in duration.
Notes:
1. Setting the BUS_CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 Mode requires that BUS_CYCLE is set to a value
greater than 1.
3. BUS_CYCLE produces no effect in eZ80 mode.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States