EZ80F91MCU Datasheet, PDF (167/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
148
3
0
OC1_INIT
1
2
0
OC0_INIT
1
1
0
MAST_MODE ₁
0
0
OC_EN
1
OC pin cleared when initialized.
OC pin set when initialized.
OC pin cleared when initialized.
OC pin set when initialized.
OC pins are independent.
OC pins all mimic OC0.
OUTPUT COMPARE mode is disabled.
OUTPUT COMPARE mode is enabled.
Timer Output Compare Control Register 2
The Timer3 Output Compare Control Register 2, detailed in Table 67, is used to
select the event that will occur on the output compare pins when a timer compare
happens.
Table 67. Timer Output Compare Control Register 2
(TMR3_OC_CTL2 = 0081h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:6]
OC3_MODE
[5:4]
OC2_MODE
Value
00
01
10
11
00
01
10
11
Description
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC3_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC2_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
PS019209-0504
PRELIMINARY
Programmable Reload Timers