EZ80F91MCU Datasheet, PDF (371/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
352
External I/O Read Timing
Figure 66 and Table 238 diagram the timing for external I/O reads. PHI clock rise/
fall to signal transition timing is independent of the particular bus mode employed
(eZ80, Z80, Intel, or Motorola).
PHI
ADDR[23:0]
T_CLK
T₁
DATA[7:0]
(input)
CSx
IORQ
RD
T₅
T₇
T₉
Figure 66. External I/O Read Timing
T₂
T₃
T₄
T₈
T₈
T₁₀
Table 238. External I/O Read Timing
Parameter Abbreviation
T₁
PHI Clock Rise to ADDR Valid Delay
T₂
PHI Clock Rise to ADDR Hold Time
T₃
Input DATA Valid to PHI Clock Rise Setup Time
T₄
PHI Clock Rise to DATA Hold Time
T₅
PHI Clock Rise to CSx Assertion Delay
T₆
PHI Clock Rise to CSx Deassertion Delay
T₇
PHI Clock Rise to IORQ Assertion Delay
Delay (ns)
Min
—
2.2
0.2
0.9
2.6
2.4
2.6
Max
6.8
—
—
—
10.8
8.8
7.0
PS019209-0504
PRELIMINARY
Electrical Characteristics