EZ80F91MCU Datasheet, PDF (345/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
326
PLL Control Register 1
The PLL is enabled using this register. PLL lock-detect status, the PLL interrupt
signals and the PLL interrupt enables are accessed via this register. A brief
description of each of these PLL Control Register 1 attributes is listed below, and
further described in Table 208.
Lock Status (LCK_STATUS). The current lock bit out of the PLL is synchronized
and can be read via this bit.
Interrupt Lock (INT_LOCK). This signal feeds the interrupt line out of the CLKGEN
module and indicates that a rising edge on the lock signal out of the PLL has been
observed.
Interrupt Unlock (INT_UNLOCK). This signal feeds the interrupt line out of the clk-
gen module and indicates that a falling edge on the lock signal out of the PLL has
been observed.
Interrupt Lock Enable (INT_LOCK_EN). This signal enables the interrupt lock bit.
Interrupt Unlock Enable (INT_UNLOCK_EN). This signal enables the interrupt
unlock bit.
PLL Enable (PLL_ENABLE). Enables/disables the PLL.
.
Table 208. PLL Control Register 1
(PLL_CTL1 = 005Fh)
Bit
7
6
Reset
0
0
CPU Access
R
R
Note: R = Read Only; R/W = Read/Write.
5
4
3
2
1
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Position
[7:6]
5
LCK_STATUS
4
INT_LOCK
Value Description
00 Reserved
0
PLL is currently out of lock.
1
PLL is currently locked.
0
Lock signal from PLL has not risen since last time register
was read.
1
Interrupt generated when PLL enters lock mode. Held until
register is read.
PS019209-0504
PRELIMINARY
Phase-Locked Loop