EZ80F91MCU Datasheet, PDF (205/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
186
UART Interrupts
There are six different sources of interrupts from the UART. The six sources of
interrupts are:
• Transmitter (two different interrupts)
• Receiver (three different interrupts)
• Modem status
UART Transmitter Interrupt
A Transmitter Hold Register Empty interrupt is generated if there is no data avail-
able in the hold register. By the same token, a transmission complete interrupt is
generated after the data in the shift register is sent. Both interrupts can be dis-
abled using individual interrupt enable bits, or cleared by writing data into the
UARTx_THR register.
UART Receiver Interrupts
A receiver interrupt can be generated by three possible events. The first event, a
receiver data ready interrupt event, indicates that one or more data bytes are
received and are ready to be read. Next, this interrupt is generated if the number
of bytes in the receiver FIFO is greater than or equal to the trigger level. If the
FIFO is not enabled, the interrupt is generated if the receive buffer contains a data
byte. This interrupt is cleared by reading the UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt
is generated when there are fewer data bytes in the receiver FIFO than the trigger
level and there are no Reads and Writes to or from the receiver FIFO for four con-
secutive byte times. When the receiver time-out interrupt is generated, it is
cleared only after emptying the entire receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share
an interrupt enable bit. The third source of a receiver interrupt is a line status error,
indicating an error in byte reception. This error can result from:
• Incorrect received parity
Note: For 9-bit data, incorrect parity indicates detection of an address byte.
• Incorrect framing (i.e., the stop bit) is not detected by receiver at the end of the
byte
• Receiver overrun condition
• A BREAK condition being detected on the receive data input
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter