EZ80F91MCU Datasheet, PDF (254/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
235
When AAK is cleared to 0, a NACK is sent when a data byte is received in MAS-
TER or SLAVE mode. If AAK is cleared to 0 in SLAVE TRANSMIT mode, the byte
in the I2C_DR register is assumed to be the final byte. After this byte is transmit-
ted, the I²C block enters the C8h state, then returns to an idle state. The I²C mod-
ule does not respond to its slave address unless AAK is set to 1. See Table 127.
Table 127. I²C Control Register
(I2C_CTL = 00CBh)
Bit
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
CPU Access
R/W R/W R/W R/W R/W R/W R
R
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
IEN
6
ENAB
5
STA
4
STP
3
IFLG
2
AAK
[1:0]
Value
0
1
0
1
Description
I²C interrupt is disabled.
I²C interrupt is enabled.
The I²C bus (SCL/SDA) is disabled and all inputs are
ignored.
The I²C bus (SCL/SDA) is enabled.
0
Master mode START condition is sent.
1
Master mode start-transmit START condition on the bus.
0
Master mode STOP condition is sent.
1
Master mode stop-transmit STOP condition on the bus.
0
I²C interrupt flag is not set.
1
I²C interrupt flag is set.
0
Not Acknowledge.
1
Acknowledge.
00 Reserved.
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface