EZ80F91MCU Datasheet, PDF (64/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
45
Table 3. Register Map (Continued)
Address
(hex) Mnemonic
Name
Reset
CPU Page
(hex) Access #
Chip Select/Wait State Generator, continued
00B2 CS3_UBR
Chip Select 3 Upper Bound Register
00
00B3 CS3_CTL
Chip Select 3 Control Register
00
R/W
94
R/W
95
Random Access Memory Control
00B4 RAM_CTL
RAM Control Register
80
00B5 RAM_ADDR_U
RAM Address Upper Byte Register
FF
00B6 MBIST_GPR
General Purpose RAM MBIST Control 00
00B7 MBIST_EMR
Ethernet MAC RAM MBIST Control
00
R/W 102
R/W 103
R/W 104
R/W 104
Serial Peripheral Interface
00B8 SPI_BRG_L
SPI Baud Rate Generator Register—
02
Low Byte
00B9 SPI_BRG_H
SPI Baud Rate Generator Register—
00
High Byte
00BA SPI_CTL
SPI Control Register
04
00BB SPI_SR
SPI Status Register
00
00BC SPI_TSR
SPI Transmit Shift Register
XX
SPI_RBR
SPI Receive Buffer Register
XX
Infrared Encoder/Decoder
00BF IR_CTL
Infrared Encoder/Decoder Control
00
R/W 215
R/W 215
R/W 216
R
217
W
218
R
218
R/W 207
Universal Asynchronous Receiver/Transmitter 0 (UART0)
00C0 UART0_RBR
UART 0 Receive Buffer Register
XX
R
192
UART0_THR
UART 0 Transmit Holding Register
XX
W
191
UART0_BRG_L
UART 0 Baud Rate Generator
Register—Low Byte
02
R/W 190
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
out reset, the Watch-Dog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read Only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a
an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.
5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
PS019209-0504
PRELIMINARY
Register Map