EZ80F91MCU Datasheet, PDF (147/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
128
Basic Timer Operation
Basic timer operation is controlled by a timer control register and a programmable
reload value. The CPU uses the control register to set up the prescaling, the input
clock source, the end-of-count behavior, and to start the timer. The 16-bit reload
value is used to determine the duration of the timer’s count before either halting or
reloading.
After choosing a timer period and writing the appropriate values to the reload reg-
isters, the CPU must set the timer enable bit (TMRx_CTL[TIM_EN]), allowing the
count to begin. The reload bit (TMRx_CTL[RLD]) should also be asserted so that
the timer counts down from the reload value, rather than from 0000h. On the sys-
tem clock cycle, after the assertion of the reload bit, the timer loads with the 16-bit
reload value and begins counting down. The reload bit is automatically cleared
after the loading operation. The timer can be enabled and reloaded on the same
cycle; however, the timer does not require disabling to reload; reloading can be
performed at any time. It is also possible to halt the timer by deasserting the timer
enable bit and resuming the count at a later time from the same point by reassert-
ing the bit.
Reading the Current Count Value
The CPU can read the current count value while the timer is running. Because the
count is a 16-bit value, the hardware latches the value of the upper byte into tem-
porary storage when the lower byte is read. This value in temporary storage is the
value returned when the upper byte is read. Therefore, the firmware should read
the lower byte first. If it attempts to read the upper byte first, it does not obtain the
current upper byte of the count. Instead, it obtains the last latched value. This
Read operation does not affect timer operation.
Setting Timer Duration
There are three factors to consider when determining Programmable Reload
Timer duration: clock frequency, clock divider ratio, and initial count value. Mini-
mum duration of the timer is achieved by loading 0001h. Maximum duration is
achieved by loading 0000h, because the timer first rolls over to FFFFh, then con-
tinues counting down to 0000h before the end-of-count is signaled. Depending
upon the TMRx_CTL[CLK_SEL] bits of the control register, the clock is either the
system clock, the on-chip RC oscillator output or an input from a pin.
The time-out period of the timer is returned by the following equation:
Clock Divider Ratio x Reload Value
Time-Out Period =
System Clock Frequency
PS019209-0504
PRELIMINARY
Programmable Reload Timers