DRA722_17 Datasheet, PDF (98/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
SIGNAL NAME
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs0
gpmc_cs1
gpmc_cs2
gpmc_cs3
gpmc_cs4
gpmc_cs5
gpmc_cs6
gpmc_cs7
gpmc_clk⁽¹⁾⁽²⁾
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
gpmc_ben0
gpmc_ben1
gpmc_wait0
gpmc_wait1
Table 4-9. GPMC Signal Descriptions (continued)
DESCRIPTION
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC Chip Select 4 (active low)
GPMC Chip Select 5 (active low)
GPMC Chip Select 6 (active low)
GPMC Chip Select 7 (active low)
GPMC Clock output
GPMC address valid active low or address latch enable
GPMC output enable active low or read enable
GPMC write enable active low
GPMC lower-byte enable active low
GPMC upper-byte enable active low
GPMC external indication of wait 0
GPMC external indication of wait 1
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
O
O
O
O
O
I
I
BALL
R3 / K7 / P2
T2 / M7 / P1
U2 / J5 / N2
U1 / K6 / R6
P3 / J7 / E1
R2 / J4 / H7
K7 / J6
M7 / H4
J5 / H5
K6 / H6
F6 / J7 / N1 / P2
D3 / J4 / P1
E6 / J6 / N2
F5 / H4 / R6
G1 / H5 / E1 / H7
T1
H6
P2
P1
N6
M4
N1
P7
P7
N1
M5
M3
N6
M4
N2
P7 / N1
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See Table 7-23 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 7-25
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
98
Terminal Configuration and Functions
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